Elementary floating point cordic function processor and shifter

ABSTRACT

Three arithmetic units including three shifters are operated in parallel and controlled by a microprogram stored in a read-only memory to provide an improved elementary function floating-point processor. The microprogram includes a set of routines for calculating 20 elementary functions including arithmetic, exponential, hyperbolic, logarithmic, square root, and trigonometric functions. Each shifter is capable of reading a fixed plural number of consecutive bits, beginning with any bit position, from an associated data storage register.

United States Patent [191 Walther ELEMENTARY FLOATING POINT CORDIC FUNCTION PROCESSOR AND SI-IIFTER [75] Inventor: John S. Walther, Sunnyvale, Calif. [73] Assignee: Hewlett-Packard Company, Palo OTHER PUBLICATIONS J. Volder, The Cordic Trigonometric Computing Shifter em x nsmsrs ls ADDER m0 SUBTRACTER SIGN OF 1 SIGN OF} DECISlON SIGNALS y REGISTER [111 3,766,370 [4 1 Oct. 16, 1973 Technique, IRE Trans. on Electronic Computers, Sept. 1959. PP. 330-334.

Primary Examiner-Charles E. Atkinson Assistant ExaminerDavid H. Malzahn Attorney-Roland I. Griffin 5 7] ABSTRACT Three arithmetic units including three shifters are operated in parallel and controlled by a microprograrn stored in a read-only memory to provide an improved elementary function floating-point processor. The miqr prcg amlicludesa s t of r u ne fic lsau a n 20 elementary functions including arithmetic, exponentia], hyperbolic, logarithmic, square root, and trigonometric functions. Each shifter is capable of reading a fixed plural number of consecutive bits, beginning with any bit position, from an associated data storage register.

5 Claims, 234 Drawing Figures Adde Control ADDER scam/1cm:

ADDER SUBTRACTEH HARDWARE BLOCK DiAGRAM M PAIENIEDum 16 I975 MEI 01 OF 233 S=Shoded Area P:

ANGLE A AND RADIUS R OF THE VECTOR P (x,y

PAIENIEDnm 16 ms 3. 766370 sum 03 I1 233 Shifter Adder Control Control 28 Q SHIFTER I x REGISTER l6 ADDER mcr SUBTRACTER 30 I2 F+E sm TER I 24 y REGISTER 1 ADDER/ SUBTRACTER DECISION 0F y S'IGNALS SIGN 0F;

20 ADDER SUBTRACTER co-smms a F READ- O NLY 34 MEMORY HARDWARE BLOCK DIAGRAM FIG.3

FLOWCHART OF THE MICROPROGRAM CONTROL FIG.4

PAIENIEBIICHBIQH 3,756,370

sum 0') BF 233 BASIC FPP OPERATIONS A. UNARY FUNCTION ROUTINES MEMORY COMPUTFR INSTR FLOATING POINT PROCESSOR UNIT FLG ER INTERFACE R CONTROLLER Pc LOG; -m

5 E 48'BIT REGiSTERS Al a II I l l Bl E If I 1 IX C I" I I I .SNX OPCODE j (4 FIG] B. BINARY FUNCTION Rourmes MEMORY COMPUTER FLOATING PomT V V PROCESSOR Ul/IT A FLG/ERR INTERFACE Lowe RON CONTROLLER o A 242 3 E 48-5|TREGISTR$ Al 27! I l W Bl HI 1 1 clrwml l I 7 4 M I l ADX oPcooe (D Q FIG.8

Pmmenw 16 ms 3; 766370 um 12 OF 233 FIGOA F1698 FIGJO PATENTEUUBT 16 I973 SI'EET 17 HF 233 INDICATES TOP EDGE CONNECTOR UPPER HALF OF ROM LOWER HALF OFROM DE! mmw H 5uw:mm5a7e M 4 M 5 E. 0:. M WES-I SHRBM-$871 M 1% m 9 2 79 m u 5HE6ME876 mm FIG. HE

PAIENTEDnm 15 I975 SHEET 18 0F 233 FIGJIA FIG. HB

FIG. HC

FIGHD FIGHE FIG. 12

PAIENIEUBBI 161975 3166370 SHEET 19 0F 233 NOTES I. *INDICATES PIN NOT CONNECTED ON THIS MICROCIRCUIT PACKAGE.

2.ALL RESISTORS ARE 560 OHMS.

3.ROM Pc WIRING SHOWN IN SIMPLIFIED FORM ABOVE.

ACTUAL WIRING OF EACH PACKAGE IS AS SHOWN BELOW.

cwma gag ADDRESS CONTENTS FIG. I5 

1. A floating point CORDIC processor for calculating trigonometric, hyperbolic, and linear elementary functions, said floating point CORDIC processor comprising: input means for receiving input information and input control signals; output means for providing output information and output control signals; first, second, and third arithmetic units coupled in parallel for performing floating point CORDIC calculAtions, each of said first, second, and third arithmetic units including an addersubtractor, a data register, and a fixed plural-bit shifting unit; coupling means for selectively intercoupling the addersubtractors, the data registers, and the fixed plural-bit shifting units of the first, second, and third arithmetic units; storage means for storing a plurality of floating point CORDIC routines and a plurality of tables of uniquely determined floating point CORDIC constants; and control means coupled to the first, second, and third arithmetic units, to the storage means, and to the coupling means, said control means being responsive to the input control signals and to the input information for selecting different ones of the floating point CORDIC routines and associated floating point CORDIC constants stored in the storage means and for selectively enabling different portions of the coupling means.
 2. A floating point CORDIC processor as in claim 1 wherein: said tables of uniquely determined floating point CORDIC constants stored in the storage means include tables of plural-bit rotation and distortion constants for use in performing trigonometric and hyperbolic floating point CORDIC calculations; said control means includes first logic means coupled to the first, second, and third arithmetic units for automatically reselecting a plural-bit rotation or distortion constant when, within the accuracy of the floating point CORDIC processor, the bits of that constant are identical to the bits of the next plural-bit rotation or distortion constant to be selected; and said control means includes second logic means coupled to the first, second, and third arithmetic units for automatically reselecting a prescribed set of plural-bit distortion constants for converging hyperbolic floating point CORDIC rountines.
 3. A floating point CORDIC processor as in claim 1 wherein said coupling means comprises: first coupling means for intercoupling the adder-subtractor of the first arithmetic unit with the data register and the fixed plural-bit shifting unit of the first arithmetic unit, with the fixed plural-bit shifting unit of the second arithmetic unit, with the adder-subtractor and the fixed plural-bit shifting unit of the third arithmetic unit for transmitting information and control signals therebetween; second coupling means for intercoupling the adder-subtractor of the second arithmetic unit with the adder-subtractor and the fixed plural-bit shifting unit of the first arithmetic unit, with the data register and the fixed plural-bit shifting unit of the second arithmetic means, and with the adder-subtractor of the third arithmetic unit for transmitting information and control signals therebetween; and third coupling means for intercoupling the adder-subtractor of the third arithmetic unit with the data register and the fixed plural-bit shifting unit of the third arithmetic unit for transmitting information and control signals therebetween.
 4. Apparatus for shifting in parallel a fixed plural number of consecutive bits beginning with any bit position from an ordered set of bits, said apparatus comprising: first logic means for defining a first plurality of overlapping groups of consecutive bits from the ordered set of bits, each of these groups comprising a predetermined number of consecutive bits beginning with a different bit position in the ordered set of bits, the number of bits in each of these groups being less than the number of bits in the ordered set of bits and being greater than the fixed plural number of consecutive bits to be shifted in parallel from the ordered set of bits; first decoding means coupled to the first logic means for selecting any one of the first plurality of overlapping groups of consecutive bits from the ordered set of bits in response to an input control signal; second logic means coupled to the first logic means for defining a second plurality of overlapping groups of consecutive bits from the group of consecutive bits selected by the first decoding means, each of these groups comprising a predetermined number of consecutive bits beginning with a different bit position in the group of consecutive bits selected by the first decoding means, the number of bits in each of these groups being less than the number of bits in the group of consecutive bits selected by the first decoding means and being equal to the fixed plural number of consecutive bits to be shifted in parallel from the ordered set of bits; second decoding means coupled to the second logic means for selecting any one of the second plurality of overlapping groups of consecutive bits in response to an input control signal; and output means coupled to the second logic means for out-putting in parallel the group of consecutive bits selected by the second decoding means.
 5. Apparatus for shifting in parallel a fixed plural number of consecutive bits beginning with any bit position from an ordered set of bits, said apparatus comprising: logic means for defining a plurality of overlapping groups of consecutive bits from the ordered set of bits, each of these groups comprising a predetermined number of consecutive bits beginning with a different bit position in the ordered set of bits, the number of bits in each of these groups being less than the number of bits in the ordered set of bits and being equal to the fixed plural number of consecutive bits to be shifted in parallel from the ordered set of bits; decoding means coupled to the logic means for selecting any one of the plurality of overlapping groups of consecutive bits from the ordered set of bits in response to an input control signal; and output means coupled to the logic means for outputting in parallel the group of consecutive bits selected by the decoding means. 